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Silicon Labs /Series0 /EZR32HG /EZR32HG220F64R61 /IDAC0 /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (CURSINK)CURSINK 0 (MINOUTTRANS)MINOUTTRANS 0 (OUTEN)OUTEN 0 (OUTMODE)OUTMODE 0 (OUTENPRS)OUTENPRS 0 (PRSCH0)PRSSEL

PRSSEL=PRSCH0

Description

Control Register

Fields

EN

Current DAC Enable
CURSINK

Current Sink Enable
MINOUTTRANS

Minimum Output Transition Enable
OUTEN

Output Enable
OUTMODE

Output Modes
OUTENPRS

PRS Controlled Output Enable
PRSSEL

IDAC Output PRS channnel Select

0 (PRSCH0): PRS Channel 0 selected.

1 (PRSCH1): PRS Channel 1 selected.

2 (PRSCH2): PRS Channel 2 selected.

3 (PRSCH3): PRS Channel 3 selected.

4 (PRSCH4): PRS Channel 4 selected.

5 (PRSCH5): PRS Channel 5 selected.

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data